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74LCX16374A
LOW VOLTAGE 16-BIT D-TYPE FLIP FLOP (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
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5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: fMAX = 170 MHz (MIN.) at VCC = 3V POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16374 LATCH-UP PERFORMANCE EXCEEDS 500mA ESD PERFORMANCE: HBM >2000V; MM > 200V
T (TSSOP48 Package) ORDER CODES : 74LCX16374AT
PIN CONNECTION
DESCRIPTION The LCX16374A is a low voltage CMOS 16-BIT D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 16 bit D-Type flip-flops are controlled by two clock inputs (nCK) and two output enable inputs (nOE). On the positive transition of the (nCK), the nQ outputs will be set to the logic state that were setup at the nD inputs. While the (nOE) input is low, the 8 outputs (nQ) will be in a normal state (high or low logic level) and while high level the outputs will be in a high impedance state. Any output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
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74LCX16374A
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 1 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 24 25 36, 35, 33, 32, 30, 29, 27, 26 47, 46, 44, 43, 41, 40, 38, 37 48 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 SYMBOL 1OE 1Q0 to 1Q7 2Q0 to 2Q7 2OE 2CK 2D0 to 2D7 1D0 to 1D7 1CK GND VCC NAME AND FUNCT ION 3 State Output Enable Input (Active LOW) 3 State Outputs 3 State Outputs 3 State Output Enable Input (Active LOW) Clock Input (LOW to HIGH, edge triggered) Data Inputs Data Inputs Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positive Supply Voltage
IEC LOGIC SYMBOLS
TRUTH TABLE
INPUT S OE H L L L
X:"H" or "L" Z: High Impedance
OUTPUTS D X X L H Q Z NO CHANGE L H
CK X
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LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO VO IIK IOK IO ICC orIGND Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (OFF state) DC Output Voltage (High or Low State) (note1) DC Input Diode Current DC Output Diode Current (note2) DC Output Source/Sink Current DC VCC or Ground Current Per Supply Pin Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to + 7.0 -0.5 to + 7.0 -0.5 to + 7.0 -0.5 to VCC + 0.5 - 50 50 50 100 -65 to +150 300 Unit V V V V mA mA mA mA
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C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) IO absolute maximum rating must be observed 2) VO < GND, VO > VCC
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO VO IOH, IOL IOH, IOL Top dt/dv Input Voltage Output Voltage (OFF state) Output Voltage (High or Low State) High or Low Level Output Current (VCC = 3.0 to 3.6V) High or Low Level Output Current (VCC = 2.7 to 3.0V) Operating Temperature: Input Transition Rise or Fall Rate (V CC = 3.0V) (note 2) Parameter Supply Voltage (note 1) Value 2.0 to 3.6 0 to 5.5 0 to 5.5 0 to VCC 24 12 -40 to+85 0 to 10 Unit V V V V mA mA
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1) Truth Table guaranteed: 1.5V to3.6V 2) VIN from0.8V to 2.0V
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DC SPECIFICATIONS
Symb ol Parameter V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 2.7 to 3.6 2.7 to 3.6 2.7 3.0 VOL Low Level Output Voltage 2.7 to 3.6 2.7 3.0 3.0 II IOZ Ioff ICC Input Leakage Current 3 State Output Leakage Current Power Off Leakage Current Quiescent Supply Current 2.7 to 3.6 2.7 to 3.6 0 2.7 to 3.6 VI = VIH or VIL VI = VIH or VIL IO=-100 A IO=-12 mA IO=-18 mA IO=-24 mA IO=100 A IO=12 mA IO=16 mA IO=24 mA VI = 0 to 5.5 V VI = VIH orVIL VO = 0 to 5.5V VI orVO = 5.5V(per pin) VI = VCC orGND VI orVO = 3.6 to 5.5V ICC ICC incr. per input 2.7 to 3.6 VIH = VCC -0.6V Test Co nditi ons Value -40 to 85 o C Min. 2.0 0.8 VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 5 10 20 20 500 A A A A A V V Max. V V Un it
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol Parameter V CC (V) VOLP VOLV Dynamic Low Voltage Quiet Output (note 1) 3.3 CL = 50 pF VIL = 0 V VIH = 3.3V Test Con dition s Min . Value T A = 25 o C T yp. 0.8 -0.8 V Max. Un it
1) Number ofoutputs defined as "n". Measured with"n-1" outputs switching from HIGH to LOW or LOW t o HIGH. The remaining output is measured in the LOW state.
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74LCX16374A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 2.5 ns)
Symb ol Parameter V CC (V) tPLH tPHL tPZL tPZH tPLZ tPHZ ts th tw fMAX tOSLH tOSHL Propagation Delay Time Output Enable Time to HIGH and LOW level Output Disable Time from HIGH and LOW level Setup Time, HIGH or LOW level Dn to CK Hold Time, HIGh or LOW level Dn to CK CK Pulse Width, HIGH or LOW Clock Pulse Frequency Output to Output Skew Time (note 1, 2) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 Test Con dition Waveform Value -40 to 85 o C Min. Max. 1.5 8.0 1.5 1.5 1.5 1.5 1.5 2.5 2.5 1.5 1.5 4.0 3.0 170 1.0 7.0 8.2 7.2 8.2 7.2 Un it
1 2 2 1 1 3 1
ns ns ns ns ns ns MHz ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Symb ol Parameter V CC (V) CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 3.3 3.3 3.3 VIN = 0 to VCC VIN = 0 to VCC fIN = 10MHz VIN = 0 or VCC Test Co nditi ons Min. Valu e T A = 25 oC T yp. 7 8 20 Max. pF pF pF Un it
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. Average operting current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/16 (per circuit)
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74LCX16374A
TEST CIRCUIT
T EST tPLH , tPHL tPZL , tPLZ tPZH , tPHZ
CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500 orequivalent RT = ZOUT of pulse generator (typically 50)
SW IT CH Open 6V GND
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cicle)
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WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cicle)
WAVEFORM 3: PULSE WIDTH
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TSSOP48 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.17 0.09 12.4 7.95 6.0 12.5 8.1 6.1 0.5 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.27 0.20 12.6 8.25 6.2 0.002 0.335 0.0067 0.0035 0.408 0.313 0.236 0.492 0.319 0.240 0.0197 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.011 0.0079 0.496 0.325 0.244
DIM.
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A2 A1 b e K c L E
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PIN 1 IDENTIFICATION
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74LCX16374A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com .
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